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| == CS 451 Architecture ==
| | This page contains information about conferences that ISU CS students sometimes attend, and journals or publication venues that ISU students sometimes submit papers to. |
| == Catalog Description ==
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| Data representation, number systems and codes, gates and logic, combinational logic, sequential circuits, flip-flops, memory and storage, computer organization, microprogramming, architectures of supercomputers and micros. Prerequisite - C or better in CS 202 and CS 303.
| | == Conferences == |
| | * [https://www.ccsc.org/midwest CCSC - Consortium for Computing Sciences in Colleges] |
| | * [https://www.indianaacademyofscience.org/annual-meeting Indiana Academy of Sciences] |
| | * [https://www.cur.org/what/events/students/ National Conference on Undergraduate Research] |
| | * [https://www.rose-hulman.edu/class/ma/web/mathconf/ Rose-Hulman Undergraduate Math Conference] |
| | * [https://inlsamp.org/ LSAMP] (underrepresented in science) |
| | * [https://www.nchchonors.org/events/nchc18 National Collegiate Honors Council] |
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| == Prerequisites == | | == Publications == |
| Student must have knowledge of Programming and Elementary Data Structures and
| | * [https://www.ccsc.org/publications/ Journal of CCSC] |
| Boolean Algebra and Logic.
| | * [https://www.indianaacademyofscience.org/publications/proceedings Proceedings of IAS] |
| | * [https://scholar.rose-hulman.edu/rhumj/ Rose-Hulman Undergraduate Mathematics Journal] |
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| == Standard Content == | | == Recent ISU CS Presentations and Posters == |
| ===Course Outline ===
| | [http://cs.indstate.edu/info/posters/ CS Student Posters] |
| The course begins with a review of Logic Circuit Design: Combinational Circuits and Sequential Circuits. Covered topics include logic gates, decoders , encoders, multiplexers, ROMs, universal gates, adders, flip-flops, latches, Karnaugh Maps, equivalent states, counters, bit pattern detectors, incrementers, multipliers, etc.
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| This is followed by the discussion of Instruction Set Architectures, and an example architecture: The Relatively Simple Computer. Basic Computer System Organization is considered : CPU, Memory, I/O units, Buses, Linear ad Two dimensional memory organizations.
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| Hardware description using RTL and methods of implementing RTL code are described.
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| Next is the coverage of CPU Design: Registers, Instruction Sets, State diagrams, RTL Code, design of
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| register section, control units, ALUs, and generation of control signals are covered. This is the hardwired control approach.
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| Also covered are Microprogrammed Control and its variations: Horizontal Microcode, Vertical Microcode, and string control signals in the ROM.
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| Next comes the coverage of Cache memory organization, and virtual memory. Topics covered are associative memory, and the associative , direct and set associative mappings and LRU and FIFO cache replacement strategies, and a simulation and estimation of hit ratios. Paging is covered in detail for implementing virtual memory, and a brief coverage of segmentation is provided.
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| Input/output is considered: polling, wait states, interrupt driven I/O, vectored interrupts, and Daisy Chaining, DMA transfers and transfer modes and I/O channels are covered.
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| CISC and RISC computers and pipelining are covered next.
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| Finally, an introduction to parallel and alternative computer architectures is given.
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| ===Learning Outcomes===
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| A knowledge of the working of a simple computer.
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| ===Important Assignments and/or Exam Questions===
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| Assignments include chapter summaries of textbook chapters ; pencil and paper quizzes are given over the course content.
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| === Standard resources ===
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| Computer Systems Organization and Architecture by John D. Carpinelli (Addison-Wesley, 2000, ISBN-10: 0-201-61253-4)
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